1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having the function of executing a pre-charge operation of a single phase data bus when data is transferred to this data bus from a plurality of driver circuits, such as data bus amplifiers, connected to the single phase data bus. Semiconductor integrated circuits of recent types such as a synchronous dynamic random access memory (hereinafter abbreviated to "SDRAM") are required to operate in synchronism with a high-speed clock of 100 MHz or more than 100 MHz, for example. To satisfy the requirement for such high-speed operation, data transfer on a data bus must be carried out efficiently. In other words, it is necessary to reset the data bus after sampling one data, so that serial data that is transferred on the data bus can be sequentially sampled. This operation is referred to as a "pre-charge operation" of the data bus.
The present invention also relates to a semiconductor integrated circuit having a data latch function for temporarily storing the data by a pipeline control system when the data is read out from a memory cell, etc., in synchronism with a clock. Recently, the semiconductor integrated circuits such as the SDRAM are required to operate in synchronism with a high-frequency clock of 100 MHz or more than 100 MHz, as described above. To satisfy this requirement, the data in the memory cells of the semiconductor integrated circuit must be read out correctly in synchronism with the high-frequency clock. Speaking in further detail, it is necessary to arrange a plurality of latch circuits in parallel in a data read path and to execute pipeline control of the data read out from the memory cells by temporarily storing the data for each bit by these latch circuits.
2. Description of the Related Art
When the data in the memory cells of a semiconductor integrated circuit such as the SDRAM is read out, it is necessary to accurately recognize the timing at which the data is transferred to the data bus after the pre-charge operation of the data bus is completed, so as to correctly sample the data of a serial system which is transferred from an arbitrary amplifier among a plurality of data bus amplifiers for reading the data in the memory cells to the single phase data bus. Generally, the data of the data bus is sampled by a pulse of a strobe signal representing the effective period of the data on the single-phase data bus.
In order to more easily understand the problem of the semiconductor integrated circuits having the pre-charge function according to the prior art, an example of the prior art technology for sampling the data by the pulse of the strobe signal on the single-phase data bus for executing the pre-charge operation will be explained with reference to FIGS. 1 to 3 of the later-appearing "BRIEF DESCRIPTION OF THE DRAWINGS".
FIG. 1 is a block diagram showing a schematic construction of a semiconductor integrated circuit having a pre-charge function according to the prior art; FIG. 2 is a circuit diagram showing a concrete construction of a reset circuit shown in FIG. 1; and FIG. 3 is a timing chart useful for explaining the operation of FIG. 2. However, the construction of the semiconductor device and its operation will be hereby explained in the case in which the data transferred from a data bus amplifier, etc., to the data bus is sampled when the data in the memory cells of a semiconductor integrated circuit such as an SDRAM is read out.
The semiconductor integrated circuit shown in FIG. 1 includes a row decoder 210 and a column decoder 220 for selecting a specific memory cell from among a plurality of memory cells disposed in matrix, and for writing and reading data. The data read out from the specific memory cells selected by these row decoder 210 and column decoder 220 is delivered to a data bus amplifier 240 through a sense amplifier 230. The data bus amplifier 240 comprises a plurality of amplification circuits (that is, a plurality of driver circuits), and these driver circuits are connected to four data buses DB-1, DB-2, DB-3 and DB-4 for transferring the data.
Referring further to FIG. 1, the data transferred to the data buses DB-1 to DB-4 from the memory cell amplifier 240 is outputted outside the semiconductor integrated circuit through a data output buffer 250 (as output data DQ). One strobe signal line SL is disposed for four data buses DB-1 to DB-4 on the strobe signal line SL so as to output a strobe signal STR (refer to FIGS. 2 and 3) representing the effective period of the data. The semiconductor integrated circuit includes further a reset circuit 100 for executing the pre-charge operation of the data on the data buses DB-1 to DB-4 on the basis of the start timing of the strobe signal STR.
FIG. 2 shows a concrete circuit construction of this reset circuit 100. The reset circuit shown in FIG. 2 includes a NOR gate 100a to which the strobe signal STR and a specific input signal Sin are inputted, and an inverter 101 on the output side of the NOR gate 100a. Since the input signal Sin is generally set to a low voltage level ("L (Low)" level), a signal generated by inverting the voltage level of the strobe signal STR is outputted from the NOR gate 100a. The signal outputted from the NOR gate 100a is inverted by the inverter 101 and is inputted to one of the input terminals of the NAND gate 102. On the other hand, the data on the data buses DB-1 to DB-4 (output data DQ) is inputted to the other input terminal of the NAND gate 102 through the NAND gate 114.
The reset circuit shown in FIG. 2 includes a latch circuit comprising two NAND gates 103 and 104 on the output side of the NAND gate 102. Inverters 105 to 109 of a plurality of stages (for example, 5 stages) are disposed on the output side of the latch circuit. These inverters 105 to 109 of a plurality of stages have the function of adjusting the later-appearing latency time. The reset signal RST outputted from the last stage inverter 109 is inputted to the gates of a plurality of P-channel transistors 110 to 113. The sources of these P-channel transistors 110 to 113 are connected to a power source (internal power source) Vii having a positive polarity, and their drains are connected to the data buses DB-1 to DB-4, respectively. The reset signal RST described above is sent from the drains of the P-channel transistors 110 to 113 to the corresponding data buses DB-1 to DB-4.
FIG. 3 shows the operation of the reset circuit described above. While the semiconductor integrated circuit is in the read mode, data DATA of a negative pulse is transferred to a data bus of a single phase on the basis of enable signals EN1 to ENn (not shown in the drawing; see later-appearing FIG. 7) representing that the data is read out from the memory cell. A strobe signal STR of a positive pulse representing the effective period of the data DATA is transferred to a strobe signal line on the basis of the enable signal EN.
To sample the data DATA on the data bus by this strobe signal STR, a reset signal RST of a positive pulse is generated with a time margin corresponding to the pulse width of the strobe signal STR from the start timing of the pulse of the strobe signal STR (the rise edge when the pulse is the positive pulse, or the fall edge when the pulse is the negative pulse, as shown in FIG. 3). In this case, however, "Bus-Fight" (i.e., bus contention) on the data bus will occur if the pre-charge operation by the reset signal RST is executed and the data DATA rises to the high voltage level ("H" (High)" level) before the pulse of the strobe signal STR terminates and falls down.
To avoid the "Bus-Fight" on the data bus, it is necessary to secure a time margin of a certain extent between the end timing of the pulse of the strobe signal STR and the start timing of the pulse of the reset signal RST. Speaking more concretely, it is necessary to generate the reset signal RST by producing a predetermined delay time (the time corresponding to the margin) from the end timing of the strobe signal STR by a plurality of inverters 105 to 109 of a plurality stages in the reset circuit shown in FIG. 2. Therefore, the latency time corresponding to the time interval between the start of the pulse of the strobe signal STR and the start of the pulse of the reset signal RST is set to a time longer than the pulse width of the practical strobe signal. Therefore, the latency time of the data bus, that is, the data occupied time on the data bus, becomes elongated, and the operating frequency cannot be increased easily.
On the other hand, a wave pipeline control system has been employed as a typical example of the pipeline control of the data read out from the memory cells of semiconductor integrated circuits such as the SDRAM. A plurality of latch circuits referred to as "FIFO" (First-In First-Out) are disposed generally in parallel in the data read path in such a wave pipeline control system, and the control of the latency time at the time of data read-out is controlled at the portion of these latch circuits. It has been customary to execute the wave pipeline control of the data by operating a plurality of latch circuits of the FIFO after the data read out from the memory cell is determined.
An example of the conventional semiconductor integrated circuits having the data latch function by such a wave pipeline control system will be explained hereby with reference to FIGS. 4 to 6 as in "BRIEF DESCRIPTION OF THE DRAWINGS" that appears later so that the problems of the prior art system may be more readily understood.
FIG. 4 is a block diagram showing the construction of a semiconductor integrated circuit of the prior art equipped with the data latch function; FIG. 5 is a circuit diagram showing the construction of the latch circuit of the semiconductor integrated circuit of the prior art; and FIG. 6 is a timing chart useful for explaining the operation of the semiconductor integrated circuit shown in FIG. 4. In this case, the operation and construction of a semiconductor integrated circuit for executing the wave pipeline control by using the FIFO comprising three latch circuits disposed in parallel in the data read path will be explained typically.
In the semiconductor integrated circuit shown in FIG. 4, first to third latch circuits 190-1 to 190-3 for temporarily storing the data DATA of the complementary system, that are read out from a plurality of memory cells (not shown, in particular) disposed in matrix, are provided in parallel with the read path of the data DATA of the complementary system. These three latch circuits 190-1 to 190-3 have the function of latching the data DATA in the sequence of bits in synchronism with the clock and also the function of sending the data DATA in the order of latching to a data out buffer 8 by a selector 7. The latch circuits 190-1 to 190-3 and the selector 7 are generically referred to as the "FIFO".
The explanation will be given in further detail. The three latch circuits 190-1 to 190-3 serially latch, for each bit, the input data signals irdx, irdz (which generically represent the input data signals ird0x, ird0z, ird1x, ird2x and ird2z that are latched by the first to third latch circuits), that represent the data DATA of the complementary system, on the basis of the corresponding control signals pi0z, pi1z and pi2z for controlling data latch, respectively. In order to reliably latch the input data signal that is inputted next, the input data signals are reset by the corresponding reset signals drst0x, drst1x and drst2x in the inputting order to the data output buffer 8.
In FIG. 4, further, the data of the complementary system (d1x and d1z) that pass through the latch circuits 190-1 to 190-3 are sent as the output data signals d10x, d10z, d11x, d11z, d12x and d12z to the selector 7. Six output data signals d10x, d10z, d11x, d11z, d12x and d12z selected serially by this selector 7 are outputted outside the semiconductor integrated circuit through the data output buffer 8 (output data DQ). In other words, in the semiconductor integrated circuit shown in FIG. 4, the data read out from the memory cells are inputted to the first to third latch circuits 190-1 to 190-3, and are then outputted from the data output buffer 8 after the passage of a certain latency time.
FIG. 5 shows a concrete construction of each of these latch circuits 190-1 to 190-3. In the latch circuit shown in FIG. 5 (for example, the first latch circuit 190-1), a first data latch unit comprising two inverters 150 and 155 for latching one ird0x of the complementary system is disposed. On the other hand, a second data latch unit comprising two inverters 160 and 165 for latching the other input data signal ird0z is disposed, too. These first and second data latch units have the function of storing the high voltage level ("H (High)" level) or low voltage level ("L (Low)" level) in accordance with the input data signals ird0x and the input data signal ird0z of the complementary system, respectively.
These input data signals ird0x and ird0z are inputted to the corresponding first and second data latch units, respectively, through N-channel transistors 130 and 132. The drains of these N-channel transistors 130 and 132 are connected to the input side of the first and second data latch units, respectively. The source of each N-channel transistor is connected to a power source Vss on the low voltage side (for example, the ground). One (ird0x) of the input data signals of the complementary system is latched by the first data latch unit on the basis of the timing of the start of the control signal pi0z supplied through the N-channel transistor 134. The signal latched in this way is outputted from the terminal from which one (d10z) of the output data signals is outputted. The other input data signal ird0z, too, is latched by the second data latch unit on the basis of the timing of the start of the control signal pi0z supplied through the N-channel transistor 136. The signal latched in this way is outputted from the terminal from which one (d10x) of the output data signals is outputted.
In the latch circuit shown in FIG. 5, further, the reset signal drst0x is supplied to the first data latch unit through the P-channel transistor 170 in order to assuredly reset the input data signal latched by the first data latch unit before the next input data signal is inputted. On the other hand, the reset signal drst0x is supplied to the second data latch unit through the P-channel transistor 180 to assuredly reset the input data signal latched by the second data latch unit before the next input data signal is inputted. The drains of these P-channel transistors 170 and 180 are connected to the input side of the first and second data latch units, respectively, and the sources of the P-channel transistors are connected to the power source Vii on the high voltage side (for example, the internal power source).
FIG. 6 shows the operation of the semiconductor integrated circuit shown in FIG. 4. The rise timing ("L" .fwdarw."H")and the fall timing ("H".fwdarw."L") of each of the control signals pi0z, pi1z and piz must fall within the effective period of the desired data (for example, the first data D0) so that the data latch operation can be executed in the inputting order of the data DATA (the first to fourth data D0, D1, D2 and D3) inputted to the first to third latch circuits 190-1 to 190-3. Furthermore, when each of the reset signals drst0x, drst1x and drst2x (for example, the reset signal drst0x of the negative pulse) is inputted to the latch circuit, the data cannot be inputted to this latch circuit during the period in which this reset signal is supplied.
When the state of the first data D0 is not yet determined, for example, the phenomenon in which the outputs of the first and second data latch units exist at the same level (for example, both at the "L" level) will occur if the control signal pi0z rises to the "H" level, and the data that is once latched might be destroyed. The data that is once latched might be destroyed similarly if the control signals pi1z and pi2z rise to the "H" level in the case in which the second and third data D1 and D2 are not yet determined. Moreover, since there is a variance concerning the time necessary before the state of the inputted data is completely determined, it has been necessary to secure a certain margin from the time, at which the state of the data (for example, the first data D0 is determined to the time at which the control signal (for example, the control signal pi0z for controlling the first latch circuit) rises and the data latch operation is started.
When the pre-charge operation on the data bus is executed by using the reset circuit of the semiconductor integrated circuits having the pre-charge function according to the prior art, the problem occurs in that the semiconductor integrated circuit cannot be operated easily in synchronism with the high-speed clock, as explained with reference to FIGS. 1 to 3.
On the other hand, when the data latch operation is executed by a plurality of latch circuits in the conventional semiconductor integrated circuits having the data latch function, it has been necessary to secure the margin from the time at which the state of the data becomes definite to the time of the start of the data latch operation, as explained with reference to FIGS. 4 to 6. Therefore, the time delay before the data is latched by the latch circuit becomes large, and the data access time increases.